Resistive RAMs (ReRAMs) have emerged as leading candidates to displace conventional Flash memories due to their high density, good scalability, low power and high performance. Previous ReRAM designs demonstrating high performance have done so on low density arrays (such as those less than one Gigabit) while those reporting high-density arrays (such as greater than eight Gigabits) were accompanied by relatively low read and write performance.
ReRAM devices are comprised of a memory array containing a plurality of memory cells. According to well-known architecture two cells are formed as isolated cell materials, using a damascene process or the like. The single cell material is shared between two transistors underneath the variable resistance material via the respective drain terminals of the transistors. Each transistor also comprises a gate terminal and a source terminal. When one of the shared cells is being programmed, a thermal disturbance is caused in the neighboring cell due to the close proximity between neighboring gate terminals (bottom electrodes) which may cause an undesired change in stage of the affected cell.
Therefore there is a need in the art for a method of fabricating a memory device with an enlarged space between neighboring bottom electrodes to avoid thermal disturbances among neighboring memory cells.